A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic pattern generation (ATPG) tools that lead to zero-defect is still an open problem. It challenging detect all stuck-at faults reach 100% In parallel, the hardware security community has been actively involved developing solutions logic locking prevent IP piracy. locking, locks are inserted different locations of netlist modify original functionality. Unless correct key programmed into IC, circuit functions incorrectly. Unfortunately, Boolean satisfiability (SAT) based attack, introduced [1], can determine secret efficiently, and break schemes. this paper, we propose novel approach powerful SAT attack on locking. A modeled as locked gate with key, where it effectively deduce satisfiable assignment reduced backtracks under initialization attack. input determines fault. We two approaches generation. First, single targeted, corresponding one bit created. This generates per Second, consider group convert its version multiple bits. inputs obtained from tool detecting faults. Our find patterns hard-to-detect were previously undetected ATPG tools. proposed efficiently redundant well. demonstrate effectiveness ITC'99 benchmarks. results show identify stuck coverage achieved. addition, time saving becomes significant Approach 2 help reduce or remove conflicts.